Intel responds to the Epyc server threat from AMD


I do love seeing the chip market get competitive again. Intel has formally announced a new class of Xeon Scalable processors, code-named “Cascade Lake-AP” or Cascade Lake Advanced Performance, that in many ways leapfrogs the best AMD has to offer.

The news comes ahead of the Supercomputing 18 show and was likely done to avoid being drowned out in the upcoming news. It also comes one day ahead of an AMD announcement, which should be hitting the wires as you read this. I don’t think that’s a coincidence.

The Cascade Lake-AP processors come with up to 48 cores and support for 12 channels of DDR4 memory, a big leap over the old design and a leap over AMD’s Epyc server processors, as well. Intel’s current top-of-the-line processor, the Xeon Platinum 8180, has only 28 cores and six memory channels, while the AMD Epyc has 32 cores and eight memory channels.

To get to 48 cores, Intel had to do something it once derided. Cascade Lake-AP models use what is called a Multi-Chip Package (MCP) design, where the CPU is actually four CPU packages connected by a very high-speed interconnect. Last year it famously ridiculed the Epyc design as “four glued-together desktop die.” That’s how Epyc achieved 32 cores. It is four eight-core dies connected by what AMD calls Infinity Fabric.

Well, now Intel is doing it. Its most recent chips are single packages with 28 cores, and obviously the laws of physics were getting in the way. It’s easier to build smaller packages of 8-12 cores and tie them together than to build one monolithic package.

So, the Cascade Lake-AP uses a pair of 24-core packages bound by high-speed interconnects. This is a better manufacturing technique than building one big 48 core chip because if there is a flaw in one of the 48 cores, the whole chip is useless. In 24 cores, there’s less chance for something to go wrong. This translates to a cheaper chip for the customer.

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